1. Field of the Invention
The present invention relates to a serial data communication system having a plurality of data transmission paths and especially used in a semiconductor integrated circuit having an elastic buffer.
2. Description of the Related Art
A conventional synchronizing operation executed by an elastic buffer is popularly employed in the field of serial data communication. According to a communication system using the elastic buffer, a timing difference between a clock signal on a data transmission side and a clock signal on a data reception side can be controlled by removal or replication of data called an Extra symbol.
A communication system using an elastic buffer will be described below.
FIG. 1 shows an example of the communication system using the elastic buffer.
A data-transmission-side semiconductor integrated circuit IC has an output control circuit 11 and a PLL circuit 15 for generating a clock signal CLK1. The output control circuit 11 has analog circuit (parallel-serial conversion circuit or the like) arranged for, e.g., data transmission. Data DATA.X is output to a data transmission path by the analog circuit and then supplied to a data-reception-side semiconductor integrated circuit IC2.
The data-reception-side semiconductor integrated circuit IC2 has a restoration circuit 12, an elastic buffer (EB) 13, a logic circuit 14, and a PLL circuit 16. The restoration circuit 12 has an analog circuit (serial-parallel conversion circuit or the like) arranged for data reception. The restoration circuit 12 restores a clock signal CLK2.
As the clock signal CLK2, for example, a signal transmitted from the data-transmission-side semiconductor integrated circuit IC1 may be directly used.
The restored data DATA.X, the clock signal CLK2, and a clock signal CLK3 generated by the PLL circuit 16 are input to the elastic buffer 13. The elastic buffer 13, for example, as shown in FIG. 2, is constituted by, e.g., a write control circuit 17, a buffer memory 18, and a read control circuit 19.
The write control circuit 17 sequentially writes the data DATA.X at addresses ADD0, ADD2, . . . , ADD7 of the buffer memory in synchronism with the clock signal CLK2. The read control circuit 19 sequentially reads data DATA.Y from the addresses ADD0, ADD2, . . . , ADD7 of the buffer memory in synchronism with the clock signal CLK3.
The elastic buffer 13 performs a synchronizing operation by means of removal or replication of an extra symbol to cancel a difference generated between the clock signal CLK2 and the clock signal CLK3.
The data DATA.Y output from the elastic buffer 13 is supplied to the logic circuit 14.
FIGS. 3 to 5 show examples of synchronizing operations in elastic buffers.
A timing at which a synchronizing operation is performed is determined by the data-transmission-side semiconductor integrated circuit (“IC1” in FIG. 1). More specifically, the data-transmission-side semiconductor integrated circuit includes an extra symbol “Symbol” for a synchronizing operation in a part of the data DATA.X.
The elastic buffer 13 in the data-reception side semiconductor integrated circuit (“IC2” in FIG. 1) performs the following processes on the basis of the extra symbol “Symbol”.
(1) When a difference between the clock signal CLK2 and the clock signal CLK3 falls within a predetermined range, as shown in FIG. 3, the extra symbol “Symbol” is directly transmitted.
(2) The frequency of the clock signal CLK2 is higher than the frequency of the clock signal CLK3, a write speed to the buffer memory is higher than a read speed. Therefore, when the difference between the clock signal CLK2 and the clock signal CLK3 is larger than the maximum value in the predetermined range, as shown in FIG. 4, the extra symbol “Symbol” is removed.
(3) When the frequency of the clock signal CLK2 is lower than the frequency of the clock signal CLK3, the write speed to the buffer memory is lower than the read speed. Therefore, when the difference between both the clock signals CLK2 and CLK3 is larger than the maximum value in the predetermined range, as shown in FIG. 5, a extra symbol “EXT” is replicated.
In a serial data communication system using a signal transmission path, a communication system using the above elastic buffer is a very effective technique to synchronize a data-transmission-side clock signal with a data-reception-side clock signal.
However, such an elastic technique is not always useful for a serial data communication system having a plurality of transmission paths.
FIG. 6 shows an example of a serial data communication system constituted by a plurality of transmission paths using an elastic buffer.
A system having four data transmission paths 0, 1, 2, and 3 will be described below.
The data-transmission-side semiconductor integrated circuit IC1 has output control circuits (including analog circuits such as parallel-serial conversion circuits) 11-0, 11-1, 11-2, and 11-3 in response to the data transmission paths 0, 1, 2, and 3. The clock signal CLK1 generated by the PLL circuit 15 is supplied to the output control circuits 11-0, 11-1, 11-2, and 11-3.
When the data-transmission-side semiconductor integrated circuit IC1 transmits, e.g., 32-bit data, the data-transmission-side semiconductor integrated circuit IC1 divides the 32-bit transmission data into four 8-bit data. The 8-bit data are serially output to the data transmission paths 0, 1, 2, and 3 by the output control circuits 11-0, 11-1, 11-2, and 11-3, respectively.
The data-reception-side semiconductor integrated circuit IC2 has restoring circuits (including analog circuits such as parallel-serial conversion circuits) 12-0, 12-1, 12-2, and 12-3 in response to the data transmission paths 0, 1, 2, and 3. The restoration circuit 12-0, 12-1, 12-2, and 12-3 convert the serially transmitted data into parallel data and restore clock signals CLK2-0, CLK2-1, CLK2-2, and CLK2-3.
In this case, the frequencies of the restored clock signals CLK2-0, CLK2-1, CLK2-2, and CLK2-3 may be different from each other depending on various conditions in restoration, and are not completely equal to the frequency of the clock signal CLK3.
Therefore, the clock signals CLK2-0, CLK2-1, CLK2-2, and CLK2-3 are synchronized with the clock signal CLK3 by using elastic buffers 13-0, 13-1, 13-2, and 13-3.
More specifically, the elastic buffer 13-0 corresponding to the data transmission path 0 independently performs “Removing/Replicate Extra Symbol” to synchronize the clock signal CLK2-0 with the clock signal CLK3.
Similarly, the elastic buffers 13-1, 13-2 and 13-3 corresponding to the data transmission paths 1, 2 and 3 independently perform “Removing/Replicate Extra Symbol” to synchronize the clock signals CLK2-1, CLK2-2, CLK2-3 with the clock signal CLK3.
In consideration of respective signal paths corresponding to the data transmission paths 0, 1, 2, and 3, synchronizing operations are performed by the elastic buffers 13-0, 13-1, 13-2, and 13-3. However, as described above, the frequencies of the clock signals CLK2-0, CLK2-1, CLK2-2, and CLK2-3 are different from each other.
For this reason, in consideration of the relation between the signal paths corresponding to the data transmission paths 0, 1, 2, and 3, on these signal paths, “Removing/Replicate Extra Symbol” is not always performed by the elastic buffers 13-0, 13-1, 13-2, and 13-3 at once.
Therefore, the serial communication system using a plurality of transmission paths, with respect to the respective signal paths, synchronizing operations can be independently performed by the elastic buffers 13-0, 13-1, 13-2, and 13-3. However, with respect to the relation between the signal paths, a large skew may be generation in a data string due to the difference between the frequencies of the clock signals CLK2-0, CLK2-1, CLK2-2, and CLK2-3 and processes performed by the elastic buffers 13-0, 13-1, 13-2, and 13-3.
FIG. 7 shows a manner observed when an extra symbol is removed in an elastic buffer.
In the elastic buffers 13-0 and 13-2 corresponding to the data transmission paths 0 and 2, extra symbols “Symbol” are independently removed to synchronize the clock signals CLK2-0 and CLK2-2 with the clock signal CLK3.
In this case, in the elastic buffers 13-0 and 13-2, the extra symbols “Symbol” are removed. However, in the elastic buffers 13-1 and 13-3 corresponding to the data transmission paths 1 and 3, the extra symbols “Symbol” are not removed.
Therefore, after the extra symbols are removed in the elastic buffers 13-0 and 13-2, the output timings of data DATA.Y0 and DATA.Y2 are largely different from the output timings of data DATA.Y1 and DATA.Y3.